U4164A邏輯分析儀模塊

主要特性與技術(shù)指標

高達 4 Gb/s 狀態(tài)模式速度選件

四倍采樣狀態(tài)模式可以通過單一探測點提供雙閾值 4 采樣

狀態(tài)模式時鐘滯后設置

高達 10 GHz 完整存儲器深度計時模式

高達 400 Mb 存儲器深度選件（400 Mb 完整通道計時、800 Mb ? 通道計時、1.6 Gb ? 通道計時）

計時模式偏移校正接口

5 ps x 5 mV 增量的眼圖掃描技術(shù)

12.5 GHz、256K 深計時縮放

描述

U4164A 邏輯分析儀模塊提供兩個新的工作模式：四倍采樣狀態(tài)模式和 10 GHz 1/4 通道時序模式。四倍采樣狀態(tài)模式能夠從每路輸入的單一探測點在兩個獨立調(diào)節(jié)閾值上對 4 個不同位置進行采樣，意味著 U4164A 對空間的需求可以進一步減少，并滿足 DDR4、DDR5、LPDDR4 和 LPDDR5 等高數(shù)據(jù)速率信號的探測需求：4 個不同的讀和寫數(shù)據(jù)采樣位置，獨立的 2.5 Gb/s 以上數(shù)據(jù)速率上升沿/下降沿采樣。1/4 通道（10 GHz）時序模式可以支持高達 1.6 Gb 采樣/輸入。除了新的工作模式外，U4164A 邏輯分析儀模塊還包括多項新特性，能夠幫助高速數(shù)字和 DDR/LPDDR 存儲器設計工程師加快系統(tǒng)啟動和調(diào)試速度。新特性包括時序模式偏移校正控制、雙采樣狀態(tài)模式雙閾值、時鐘滯后控制（時鐘關(guān)閉后時鐘輸入存在噪聲，該特性可以調(diào)整狀態(tài)模式的噪聲靈敏度）以及非常深的存儲器選件（400 Mb 全通道，800 Mb 半通道，1.6 Gb 1/4 通道）。

Main Characteristics and Technical Indicators

Speed options up to 4 Gb/s state mode

Quadruple sampling state mode can provide double threshold 4 sampling through a single detection point

State mode clock lag setting

Up to 10 GHz full memory depth timing mode

Up to 400 Mb memory depth options (400 Mb full channel timing, 800 Mb channel timing, 1.6 Gb channel timing)

Timing mode offset correction interface

5 ps x 5 mV Incremental Eye Scanning Technology

12.5 GHz, 256K Deep Time zoom

describe

U4164A logic analyzer module provides two new working modes: quadruple sampling mode and 10 GHz 1/4 channel sequential mode. The quadruple sampling state mode can sample four different locations from a single probe point in each input channel at two independent adjusting thresholds, which means that U4164A can further reduce the demａnd for space and meet the detection requirements of high data rate signals such as DDR4, DDR5, LPDDR4 and LPDDR5: four different sampling locations for reading and writing data, and independent data over 2.5 Gb/s. Sampling along the rising/falling edge of the rate. The 1/4 channel (10 GHz) sequential mode can support up to 1.6 GB sampling/input. In addition to the new mode of operation, the U4164A logic analyzer module includes a number of new features that can help high-speed digital and DDR/LPDDR memory design engineers speed up system start-up and debugging. New features include timing mode offset correction control, double sampling state mode double threshold control, clock lag control (noise in clock input after clock closure, which can adjust the noise sensitivity of state mode) and very deep memory options (400 Mb full channel, 800 Mb half channel, 1.6 Gb 1/4 channel).