BSX320誤碼率測(cè)試儀

主要性能指標(biāo)

• 高達(dá) 32 Gb/s 的碼型發(fā)生和誤碼分析功能

• 選配內(nèi)置 4 階發(fā)射機(jī)均衡功能，支持交互式鏈路訓(xùn)練

• 面向協(xié)議和面向位的多鏈碼型定序技術(shù)，增強(qiáng)型碼型/序列編輯器

• 激勵(lì)響應(yīng)反饋，用戶自定義檢測(cè)器碼型匹配

• 已獲的誤碼定位分析技術(shù)（Error Location Analysis™ ），超越BER測(cè)量，分析關(guān)聯(lián)度和確定性錯(cuò)誤碼型，深入了解誤碼根源

• 選配前向糾錯(cuò)分析技術(shù)，根據(jù)測(cè)得誤碼位置碼型仿真FEC后誤碼率

• 集成眼圖和 BER 關(guān)聯(lián)功能，包括模板測(cè)試、抖動(dòng)峰值、BER輪廓

• 選配抖動(dòng)分離及定位 (Jitter Map) 系統(tǒng)，提供豐富的抖動(dòng)解析 – 支持長(zhǎng)碼型（如 PRBS-31）

主要特點(diǎn)

• 為接收機(jī)壓力測(cè)試、調(diào)試和一致性測(cè)試提供單一解決方案

• 測(cè)試第三代和第四代標(biāo)準(zhǔn)，包括 PCIe、SAS 和 USB3.1 及各種自主開發(fā)的標(biāo)準(zhǔn)

• 超過 16 Gb/s 的 DUT 握手功能，滿足環(huán)回發(fā)起和自適應(yīng)鏈路訓(xùn)練的接收機(jī)測(cè)試要求，支持 PCIe 等主要標(biāo)準(zhǔn)

• 協(xié)議識(shí)別碼型發(fā)生和誤碼檢測(cè)，支持靈活的激勵(lì)響應(yīng)編程能力，調(diào)試握手問題。

• 前向糾錯(cuò)(FEC)仿真選項(xiàng)，可以測(cè)量糾錯(cuò)前和糾錯(cuò)后BER，支持常用的Reed-Solomon FEC代碼。

• 為各種主要標(biāo)準(zhǔn)提供了校準(zhǔn)和測(cè)試自動(dòng)化軟件

應(yīng)用

• 設(shè)計(jì)驗(yàn)證，包括信號(hào)完整性、抖動(dòng)和時(shí)序分析

• 測(cè)試高速串行系統(tǒng)、復(fù)雜設(shè)計(jì)的性能

• 設(shè)計(jì)/驗(yàn)證高速 I/O 組件和系統(tǒng)，包括 DUT 握手

• 信號(hào)完整性分析 – 模板測(cè)試、峰值抖動(dòng)、BER輪廓、抖動(dòng)分離及定位（Jitter Map)和前向糾錯(cuò)仿真

智能內(nèi)存排序

由于面向位的內(nèi)存排序模式和協(xié)議識(shí)別內(nèi)存排序模式，另外由于能夠根據(jù)用戶自定義檢測(cè)器碼型匹配情況推進(jìn)排序器，BSX 系列允許用戶創(chuàng)建自己的基于協(xié)議的碼型和握手序列。

Key performance indicators

Up to 32 Gb/s code type generation and error code analysis function

Optional built-in 4 - stage transmitter balance function, support interactive link training

Protocol - and bit - oriented multi - chain code - type sequencing technology, enhanced code - type/sequence editor

Excitation response feedback, user - defined detector pattern matching

Error positioning Analysis technology patents (Error Location Analysis ™), beyond the BER measurement, Analysis of correlation and deterministic Error type, understａnd Error source

Forward error correction analysis technology is selected to simulate the backward error rate of FEC according to the measured error code position code type

Integration of eye map and BER association function, including template testing, jitter peak, BER contour

Optional Jitter Map system to provide rich Jitter resolution -- support for long code types (e.g. Prbs-31)

The main features

Provides a single solution for receiver pressure testing, debugging and conformance testing

Testing third and fourth generation standards, including PCIe, SAS and USB3.1, and various self-developed standards

The DUT handshake function exceeding 16 Gb/s meets the receiver test requirements of loopback initiation and adaptive link training, and supports PCIe and other major standards

Protocol identification code type occurrence and error detection, support flexible excitation response programming ability, debugging handshake problem.

Forward error correction (FEC) simulation option, can measure before and after error correction BER, support common reed-solomon FEC code.

Provides calibration and test automation software for major standards

application

Design verification, including signal integrity, jitter and timing analysis

Test the performance of high-speed serial system and complex design

Design/verify high speed I/O components and systems, including the DUT handshake

Signal integrity analysis -- template test, peak Jitter, BER contour, Jitter Map and forward error correction simulation

Intelligent memory sort

The BSX series allows users to create their own protocol based code types and handshake sequences, due to the bit-oriented memory sorting pattern and protocol recognition memory sorting pattern, and the ability to advance the sorter based on user-defined detector code type matches.