B4661A 用于邏輯分析儀的存儲(chǔ)器分析軟件

主要特性與技術(shù)指標(biāo)

DDR3、DDR4、DDR5、LPDDR2、LPDDR3、LPDDR4 和 LPDDR5 分析

使用 “事務(wù)解碼" 和 “流量概況" 視圖快速引導(dǎo)流量

在低功耗數(shù)據(jù)傳輸?shù)氖聞?wù)解碼之后的是自刷新進(jìn)入/退出、多用途命令（MPC）、DDR4 3DS（DRAM 裸片 3 維堆疊）、LPDDR5 組織模式、速度變化和模式寄存器

查看 MB 數(shù)據(jù)速率和總線利用率百分比的性能計(jì)算結(jié)果和圖形，通過(guò)圖形滾動(dòng)刷新窗口觀察刷新速率，查看頁(yè)面打開(kāi)/關(guān)閉事務(wù)關(guān)聯(lián)以及每個(gè)讀取或?qū)懭胧聞?wù)所發(fā)送的數(shù)據(jù)

顯示地址映射，查看由于刷新之間激活次數(shù)太多有出現(xiàn) Row Hammer 問(wèn)題風(fēng)險(xiǎn)的地址

DDR3、DDR4、DDR5、LPDDR2、LPDDR3、LPDDR4 和 LPDDR5 一致性驗(yàn)證

使用后期處理一致性違規(guī)工具來(lái)測(cè)試在存儲(chǔ)速度變化時(shí)的協(xié)議一致性違規(guī)

使用后期處理或?qū)崟r(shí)處理工具來(lái)識(shí)別 DDR/2/3/4/5 或 LPDDR/2/3/4/5 狀態(tài)機(jī)、協(xié)議一致性、協(xié)議級(jí)總線周期時(shí)序違規(guī)

使用實(shí)時(shí)一致性違規(guī)分析工具自動(dòng)執(zhí)行實(shí)時(shí) DDR2/3/4/5 或 LPDDR2/3/4/5 協(xié)議一致性測(cè)量和跡線捕獲，節(jié)省大量時(shí)間

后期處理工具和實(shí)時(shí)工具均提供增強(qiáng)的參數(shù)編輯界面，可以讓您輕松地編輯 DDR2/3/4/5 或 LPDDR2/3/4/5 標(biāo)準(zhǔn)預(yù)置測(cè)試的參數(shù)

ONFi（開(kāi)放式 NAND 閃存接口）分析工具

使用密集的 ONFi 分析 “時(shí)間線" 視圖，快速在多個(gè) ONFi 目標(biāo)之間進(jìn)行導(dǎo)航

使用 ONFi 事務(wù)的 “詳細(xì)信息" 視圖，將 ONFi 操作視為序列中的一組邏輯關(guān)聯(lián)命令，從而節(jié)省時(shí)間

列出用于 DDR、DDR2、DDR3、DDR4、LPDDR、LPDDR2、LPDDR3 和 LPDDR4 的

解碼 DDR、DDR2、DDR3、DDR4、LPDDR、LPDDR2、LPDDR3 和 LPDDR4 命令以及 MRS 命令

包括 DDR4 RDIMM 和 LRDIMM 的 MRS 解碼選項(xiàng)

使用用于 DDR/2/3/4 和 LPDDR/2/3 的物理地址觸發(fā)工具，快速完成物理地址觸發(fā)設(shè)置

Main Characteristics and Technical Indicators

Analysis of DDR3, DDR4, DDR5, LPDDR2, LPDDR3, LPDDR4 and LPDDR5

Quickly boot traffic using Transaction Decoding and Traffic Profile views

After transaction decoding of low power data transmission, refresh entry/exit, multi-purpose commａnd (MPC), DDR4 3DS (DRAM bare 3-D stack), LPDDR5 organization mode, speed change and mode register are implemented.

View the performance calculation results and graphics of MB data rate and percentage of bus utilization, observe the refresh rate through the graphical scroll refresh window, view the page open/close transaction Association and the data sent by each read or write transaction.

Display address maps to see addresses at risk of Row Hammer problems due to too many activations between refreshes

Conformity Verification of DDR3, DDR4, DDR5, LPDDR2, LPDDR3, LPDDR4 and LPDDR5

Using post-processing consistency violation tools to test protocol consistency violations when storage speed changes

Use post-processing or real-time processing tools to identify DDR/2/3/4/5 or LPDDR/2/3/4/5 state machines, protocol consistency, protocol-level bus cycle timing violations

Using real-time consistency violation analysis tools to automatically perform real-time DDR2/3/4/5 or LPDDR2/3/4/5 protocol consistency measurement and trace capture saves a lot of time.

Both post-processing tools and real-time tools provide enhanced parameter editing interfaces that allow you to easily edit parameters for DDR2/3/4/5 or LPDDR2/3/4/5 standard preset tests.

ONFi (Open NAND Flash Interface) Analysis Tool

Use intensive ONFi analysis of "timeline" views to quickly navigate between multiple ONFi targets

Using the "Details" view of ONFi transactions, ONFi operations are treated as a set of logically related commands in a sequence, saving time

List decoders for DDR, DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3 and LPDDR4

Decoding DDR, DDR2, DDR3, DDR4, LPDDR, LPDDR2, LPDDR3 and LPDDR4 commands and MRS commands

MRS decoding options including DDR4 RDIMM and LRDIMM

Using physical address triggering tools for DDR/2/3/4 and LPDDR/2/3, we can quickly complete the physical address triggering settings.