6DD3460-0AC0

6DD3460-0AC0

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6DD3460-0AC0

　如圖1所示，典型的16位并行閃存每秒傳輸速率為20Mb。對(duì)于使用32位微控制器和32位外部閃存通信總線的系統(tǒng)(如恩智浦產(chǎn)品)，設(shè)計(jì)人員可以選擇使用兩個(gè)16位并行閃存達(dá)到40Mb/s的傳輸速率。但是，增加速度的同時(shí)也會(huì)增加成本。這種配置使用兩個(gè)獨(dú)立的并行閃存，每個(gè)閃存有數(shù)十個(gè)封裝管腳，無(wú)論是封裝尺寸、管腳數(shù)量，還是PCB空間占用，都會(huì)遠(yuǎn)遠(yuǎn)超出設(shè)計(jì)人員的承受范圍。

　　串行閃存通常使用簡(jiǎn)單的四針串行外設(shè)接口(SPI),從空間占用、功耗和成本等因素考慮是并行閃存的理想替代產(chǎn)品，但是傳輸速率非常低。通過(guò)圖1我們可以看到典型SPI閃存50MHz的傳輸速率僅為5Mb/s，而采用兩個(gè)16位并行閃存配置系統(tǒng)的傳輸速率是其8倍。另一個(gè)問(wèn)題就是大多數(shù)微控制器SPI接口都與MCU外設(shè)矩陣連接，處理器訪問(wèn)數(shù)據(jù)前必須先由驅(qū)動(dòng)器代碼接收到內(nèi)容并保存在板載RAM中。由于每次讀取串行閃存都要通過(guò)SPI軟件層，因此速度無(wú)法提高。對(duì)于采用標(biāo)準(zhǔn)SPI接口的外部閃存應(yīng)用，速度可能無(wú)法滿足要求。

　　新型四通道SPI閃存采用改進(jìn)的6針SPI配置，數(shù)據(jù)傳輸速率遠(yuǎn)高于傳統(tǒng)的SPI接口。如圖1所示，四通道SPI每秒zui大傳輸速率可達(dá)40Mb，與兩個(gè)16位并行閃存速度相當(dāng)。由于減少了管腳數(shù)量和封裝尺寸，與并行方案相比，四通道SPI串行閃存可有效降低成本。雖然四通道SPI閃存*可替代嵌入式系統(tǒng)中的并行閃存，但目前32位微控制器設(shè)計(jì)并不支持四通道SPI閃存的zui大傳輸速率。這主要是因?yàn)樗耐ǖ繱PI接口與傳統(tǒng)的SPI接口連接方式相同，直接連接了微控制器外設(shè)矩陣。

　　解決外部閃存選型難題

　　恩智浦新開(kāi)發(fā)的SPI閃存接口(SPIFI)可以*解決并行/串行閃存的選型困擾。已申請(qǐng)的SPIFI外設(shè)可以將低成本SPI和新型四通道SPI閃存映像到ARM Cortex-M3內(nèi)存中。與外部并行閃存方案相比，使用SPI外部閃存的MCU性能損失非常小。由于外部SPI閃存完整的內(nèi)存空間可以映像到MCU內(nèi)存中，微控制器對(duì)外部閃存直接訪問(wèn)，無(wú)需使用軟件API或庫(kù)。

　　例如，使用四通道SPI閃存，SPIFI外設(shè)傳輸速率可達(dá)40Mb/s。設(shè)計(jì)人員可以選擇更便宜的SPI閃存器件，在保證性能的基礎(chǔ)上縮小腳位尺寸，簡(jiǎn)化配置。由于系統(tǒng)無(wú)需針對(duì)外部并行閃存使用龐大的接口設(shè)計(jì)，設(shè)計(jì)人員還可以選擇體積更小、成本更低的微控制器。嵌入式系統(tǒng)采用SPIFI外設(shè)可以提高內(nèi)存資源利用率，縮小尺寸，提高效率，降低系統(tǒng)總成本。

　　SPIFI外設(shè)是恩智浦LPC1800系列ARM Cortex-M3微控制器*采用的一種技術(shù)。此外，即將面市的新產(chǎn)品還包括低成本Cortex-M0系列和Cortex M4數(shù)字符串行控制器(DSC)。

　　SPIFI支持目前市場(chǎng)上大部分串行閃存器件(含四通道讀/寫(xiě)產(chǎn)品)，配置編程非常簡(jiǎn)便，采用4/6引腳設(shè)計(jì)(取決于串行閃存類型)，支持小型寄存器組，優(yōu)化內(nèi)存事務(wù)，其軟件指令可降低CPU開(kāi)銷，提高內(nèi)存數(shù)據(jù)交換效率。

　　SPIFI工作原理

　　圖2給出了SPIFI外設(shè)的功能框圖。SPIFI功能塊與微控制器應(yīng)用的高速總線(AHB)矩陣連接，后者主要用于處理器內(nèi)核和片上內(nèi)存。SPIFI將外部SPI閃存內(nèi)容映射到微控制器內(nèi)存中。當(dāng)片上ROM啟動(dòng)代碼激活SPIFI接口后，外部SPI內(nèi)存與核心處理單元上的片上內(nèi)存功能*相似。

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